First Embedded Image Processing Solution for Camera Phones


DxO Labs has made available the first embedded Image Processing Solution (ISP) for camera phones with built-in Enhanced Depth of Field (EDOF) and Optical Fault Correction. This is an innovation consisting of the new generation DxO programmable and configurable SIMD RTL core optimized for on-the-fly image processing.

First Embedded Image Processing Solution for Camera Phones

The three embedded image processing solutions come as silicon IP licensed to silicon vendors.
It is an innovation meant to allow phone designers to overcome the limitations of ever shrinking pixels used in high resolution, small form factor camera modules, and consists of merging the best digital optics technology called enhanced depth of field or EDoF, with the most advanced image processing technology based on anti-aliasing demos icing, sensor and pixel level noise compensation and
DSC-class auto exposure and auto white balance.

DxO IPE, DxO ISP and DxO DOP are the three solutions coming from SxO Labs.

The first one is a mixture between the latest digital optics technology with support for low light lens designs, enhanced depth-of-field designs and low profile lens designs with DSC-class image signal processing for the best overall low light imaging performance available.

DxO ISP offers DSC-class image processing without the digital optics implementation, while DxO DOP comes with the digital optics processing without the image processing functions.

The three solutions work on the SIMD processor core and with a flexible architecture these three come in different configurations for supporting resolutions from 1.3MP to 12MP.
CMOS imaging sensor chips will have these solutions embedded on companion chips inside camera
modules, or on baseband or application processor chips.

Together with a royalty contract and a license, DxO Labs will provide a system level, bit-accurate C model for the RTL and microcode; a hardware integration guide including external interfaces (hardware I/F, timing, registers & memories);configured RTL (obfuscated structural Verilog) with 100% coverage; verification coverage and guidelines; recommended chip test methodology; a software integration guide including Microcontroller firmware and library description; microcontroller firmware and library; one lens design which when mated to the system hardware meets the optical system specifications (for DxO DOP and DxO IPE families only); support for chip specification, RTL integration and verification, firmware integration and verification, chip backend, system level verification, lens sample manufacturing and verification, chip verification and image quality tuning; and a lens and sensor system calibration.




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